DIGITAL ELECTRONICS AND LOGIC DESIGN [ELD] EE 204 I KTU B TECH QUESTIONS FOR SECOND YEAR [S4] STUDENTS | QUESTION BANK Part - |


APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

 DIGITAL ELECTRONICS AND LOGIC DESIGN I S4 KTU
 QUESTION PAPERS

DIGITAL ELECTRONICS AND LOGIC DESIGN [ELD] EE 204 I KTU B TECH QUESTIONS FOR SECOND YEAR [S4] STUDENTS | QUESTION BANK Part - |


PART A

1.(a) Represent 125.7510 in Binary and Octal number system

(b) Perform the arithmetic operation AB616 – 74516

2. Draw and explain the operation of TTL NAND gate

3. With neat diagram, Explain the operation of BCD Adder circuit

4. How a J-K Flip flop differs from R-S Flip flop. Explain the

transition table of J-K flip flop

5. Design a synchronous 3 bit up counter using J-K flip flop

6. Compare state diagram and state table with one example

7. Implement ∑ m( 2,4,5,6,7) using PAL

PART B

8. Draw and explain the schematic of R-2R ladder DAC.

9. a) Perform 2's complement addition for -214 + 321

b) Convert the Gray code 1101 to Binary

c) State and Explain DeMorgan’s Theorems

10. a) Expand A+BC+ABD+ABCD to minterms and maxterms

b) Simplify the expression G= BD+BCD+ABC D and realize using NAND gates alone

11. Reduce the function F = ∑ m( 0,1,2,3,6,7,13,15) using K-Map

Minimize the function G =  ∑m (0,2,6,10,11,12,13 ) + d(3,4,5,14,15 )

12. a) Draw the schematic and explain a Full Adder circuit

b) Design a 2 bit Magnitude comparator circuit

13. a) Implement the function = F( a,b,c) ∑ m( 1,3,5,6) using MUX

b) How a Master slave J K flip flop is designed and set up? Explain.

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